1. Field of the Invention
The present invention relates to a monitor, and more particularly to a frame size regulating circuit for simultaneously controlling horizontal and vertical sizes of a frame.
2. Description of the Prior Art
Horizontal and vertical sizes of a frame displayed on a CRT of a monitor are determined by externally-supplied horizontal and vertical sync signals.
A conventional frame size regulating circuit of such kind is as illustrated in FIG. 1. Referring to FIG. 1, a reference numeral 1 denotes a microprocessor for providing pulsewidth modulation signals PWM1 and PWM2 for controlling horizontal and vertical sizes in accordance with input horizontal and vertical sync signals Hs and Vs; and 2 is a horizontal size determinator part for shaping and amplifying pulsewidth modulation signal PWM1 to produce a horizontal size determination signal of DC component. A reference numeral 3 denotes a mixer for overlapping the horizontal size determination signal with an externally-supplied distortion correction signal GD, and providing the overlap signal to an unshown diode modulator. A reference numeral 4 denotes a vertical size determinator part for shaping pulsewidth modulation signal PWM2 to provide a vertical size determination signal of DC component; and 5 is a deflection circuit for overlapping the vertical size determination signal with horizontal and vertical sync signals Hs and Vs to provide a deflection signal of triangular waveform.
Horizontal size determinator part 2 is formed by a shaping part 2a for shaping pulsewidth modulation signal PWM1 and an amplifying part 2b for amplifying a DC voltage of shaping part 2a.
Shaping part 2a includes a resistor 21 for biasing pulsewidth modulation signal PWM1, and resistors 23 and 25 which are serially connected with each other for distributing an externally-supplied DC power source Vcc and are connected to the output side of resistor 21 for overlapping a distribution voltage with an output voltage of resistor 21. Also, a resistor 27 biases the overlap signal and a capacitor 29 smooths a bias signal of resistor 27 for providing the DC voltage.
Meantime, amplifying part 2b includes an amplifier 31 for amplifying the DC voltage of shaping part 2a, and resistors 33 and 35 respectively connected between the output side and between the (-) port of amplifier 31 and the (-) port of amplifier 31 and a ground for determining an amplification factor of amplifier 31.
Vertical size determinator part 4 is formed by resistors 41, 43, 45 and 47 and a capacitor 49 which are identical to shaping part 2a of horizontal size determinator part 2.
When horizontal and vertical sync signals Hs and Vs are supplied into microprocessor 1 in the conventional frame size regulating circuit as described above, microprocessor 1 generates pulsewidth modulation signals PWM1 and PWM2 corresponding to horizontal and vertical sync signals Hs and Vs, in which pulsewidth modulation signal PWM1 is supplied to shaping part 2a of horizontal size determinator part 2.
Shaping part 2a shapes pulsewidth modulation signal PWM1 to provide the DC voltage which is in turn supplied to amplifying part 2b. Then, amplifying part 2b amplifies the DC voltage to provide the horizontal size determination signal of DC component.
The operation of horizontal size determinator part 2 which provides the horizontal size determination signal of DC component from pulsewidth modulation signal PWM1 will be described in more detail with reference to FIG. 2. Pulsewidth modulation signal PWM1 is supplied to resistor 21 of shaping part 2a, and resistor 21 biases pulsewidth modulation signal PWM1.
DC power source Vcc is supplied to resistors 23 and 25 which distribute DC power source Vcc and overlap the distribution voltage with the bias signal of resistor 21. The overlap signal is supplied to resistor 27 which biases the overlap signal. The bias signal of resistor 27 is supplied to capacitor 29 which then smooths the bias signal to produce the DC voltage.
The DC voltage is supplied to the (+) port of amplifier 31 in amplifying part 2b, and amplifier 31 amplifies the DC voltage to provide the horizontal size determination signal of DC component. At this time, the amplification factor of amplifier 31 is determined by resistors 33 and 35.
The horizontal size determination signal is supplied to mixer 3 which in turn overlaps the horizontal size determination signal with distortion correction signal GD. The resulting overlap signal is supplied to the diode modulation.
On the other hand, pulsewidth modulation signal PWM2 of microprocessor 1 is supplied to vertical size determinator part 4. Then, vertical size determinator part 4 shapes pulsewidth modulation signal PWM2 to generate the vertical size determination signal of DC component. Here, the procedure of generating the vertical size determination signal of DC component from pulsewidth modulation signal PWM2 is the same as executed by shaping part 2a of horizontal size determinator part 2 in which the DC voltage is generated from pulsewidth modulation signal PWM1.
Thus, the vertical size determination signal of DC component is supplied to deflection circuit 5 which overlaps the vertical size determination signal of DC component with the horizontal and vertical sync signals Hs and Vs. Thereafter, the overlap signal is oscillated to generate the deflection signal of triangular waveform.
In the frame size regulating circuit as described above, however, the horizontal and vertical sizes of the frame is determined at the initial time in accordance with the horizontal sync signal and vertical sync signal, and the initially-determined frame size cannot be simultaneously reduced nor enlarged as desired.